Integrated circuits are designed to recognize certain voltage levels as representative of boolean logic values. For instance, a high voltage may be recognized as a 1, while a low voltage may be recognized as a 0. There are multiple specifications for different types of circuitry, each of which may recognize different levels of voltages as 1's and 0's. Such specifications are very important to ensure that devices manufactured by different manufacturers will work with each other. One such specification, Low Voltage Transistor-Transistor Logic (LVTTL) is commonly used to define voltage levels recognizable by memory devices for personal computers. Dynamic Random Access Memory (DRAM) devices provide the main memory for personal computers, and accept and provide data at LVTTL levels. Input buffers or receivers in DRAMs that receive these levels have to be able to recognize whether a voltage is intended to be a high or a low voltage.
The LVTTL specification dictates that all voltages higher than Voltage Input High min(VIH min=2.0 volts) be interpreted as a high voltage, and that all voltages lower than Voltage Input Low max (VIL max=0.8 volts) be interpreted as a low voltage. In addition, it requires that output drivers of devices output voltages of specified values. Voltage Output High min (VOH min=2.4 volts) is the minimum voltage that should be output when a high logic signal is to be transmitted. Voltage Output Low max (VOL max=0.4 volts) is the maximum voltage that should be output when a low logic signal is to be transmitted. As can be seen, this provides a 0.4 volt noise margin (the differences between high and low input and output voltages) for connecting two LVTTL compliant devices.
The LVTTL specification was derived from original TTL specifications which were developed over 20 years ago. The specification provides for a 0.8 volt differential between VIL and VIH. Device speeds of today are much greater than when the specification was first developed. Personal computer processor speeds were measured in kilohertz, whereas today they are measured in hundreds of megahertz, with no apparent slowdown in the rate of increasing speed. There are several drawbacks to using LVTTL specified voltage swings in today's higher speed systems. One problem is that the large signal swings of 2.0 volts induces significant amounts of electromagnetic interference (EMI) radiation. The width of today's memory busses, 64 bits wide, greatly increases the amount of EMI emitted. There are strict controls on such radiation, and it is getting harder to meet limits imposed by government regulations.
As the operating speeds of personal computers increase, the power dissipation increases due to the large voltage transitions between high and low. The AC component of the signal switching power dissipation is approximately equal to cv.sup.2 f, where c is the capacitance in farads, v is the voltage swing in volts, and f is the frequency of the switching in hertz. When originally developed, the AC component of power dissipation was not significant for TTL circuitry, since the typical operating frequencies were much lower than today, and the dc component was high, since bipolar transistors were used. For a given physical environment, the capacitance is fixed, and therefore, the only way to reduce the AC component of power dissipation at increasing operating frequencies is to reduce the signal swing. The larger swings were necessary to provide adequate noise margin for VIH and VIL specifications.
Another drawback of using large signal swings for higher frequency operations is the increased output drive current requirements. For a driver to charge and discharge the capacitance, i=cdv/dt, where i is the current in amps, c is the capacitance in farads, and dv/dt is the voltage slew rate in volts per second. Dv is 2 v for LVTTL, and dt must get smaller as the operating frequency increases. As the operating frequency goes up, the current capability of a driver must increase. This results in larger output buffer transistor sizes, which represent a larger capacitive load to a pre-driver circuit. These larger capacitive loads force a much more difficult, high frequency pre-driver circuit design in order to drive larger currents.
Current input buffer circuits comprise in their simplest form, a series stacked p and n field effect transistor (FET) pair, M1 at 110 and M2 at 112 as shown in prior art FIG. 1. An input 114 is applied to the gates of both transistors, and only one transistor conducts in steady state, resulting in a very low DC current draw. The output is taken between the transistors at 116. The input threshold, or the input voltage at which the output of the buffer transitions to the opposite logic state, is determined by the ratio of the output impedance of M1 and M2 at a given input voltage, V1. At a given input and output voltage, the output impedance of the transistor will be a function of the physical device width, device length, the threshold voltage of the device, channel doping concentration, and gate oxide thickness. Since n and p FETs are formed using different masks, their nominal FET characteristics may change with respect to the each other for different fabrication lots. Further, the impedances have sensitivity to the drain-to-source voltage, VDS, and the bulk-to-source voltage, VBS. Given the topography of the circuit, the p-channel transistor, M1, and the n-channel transistor, M2 will experience different values of VDS and VBS for a given input voltage. Also, since the M1 and M2 transistors are of different types, changes in any of the aforementioned physical characteristics of the p-channel device will not necessarily track changes in the n-channel characteristics. Therefore, the input threshold voltage of the input buffer will vary significantly with process parameter variation and temperature. This variance requires a larger differential for VIH/VIL to guarantee proper operation.
The input buffer of FIG. 1 was selected as the standard type of input buffer for LVTTL implementation because of its low power usage in steady state conditions. Twenty years ago, with lower frequency personal computers, this was a valid design point. With increasing processor speeds, and hence a greater AC power dissipation component, the assumption is no longer valid. In a typical application, such as a memory to logic interface, the output signal becomes bandwidth limited at about 100 Mhz. It fails to output an adequate VOH min or VOL max above that frequency. This has been acceptable to date, since memory bus frequencies in personal computer range from 33 to 66 Mhz. However, there is a desire to increase the frequency of the memory bus to over 100 Mhz in order to improve system performance. Therefore, there is a need to increase the frequency response of the memory to logic interface while maintaining backwards compatibility with existing devices.
There is a need for a new signaling interface which is compatible with existing memory devices in personal computers. Consumers have many millions of dollars invested in their DRAM memory for their personal computers. Clearly, any type of new signaling technology should be backwards compatible with existing memory and memory controllers in order to preserve that investment.
Several alternative arrangements have been proposed, such as Small Swing Transistor Logic (SSTL), High Speed Transistor Logic (HSTL), and Gunning Transistor Logic (GTL). While these may solve some of the problems, they are not backward compatible with existing LVTTL devices, or they may require hundreds of additional components in a personal computer to implement. They do not protect the considerable investment of consumers. These new incompatible standards will not work properly in existing applications. Further, where the consumer upgrades their personal computer memory five years into the future, they will still require devices which are LVTTL compatible. This requirement would necessitate two different device types, an LVTTL compatible and a non-compatible, higher speed device. There is a need for a device which provides both higher speeds and is LVTTL compatible. There is also a concern over power consumption and EMI radiation in high speed computers.